The present inventions relate to a new generation of electronic microcircuit technology, having dimensions much smaller than those of semiconductor integrated circuits, and to related systems and processes.
To better explain the significance and advantages of these innovations, the following paragraphs (down to page 15) will review some technological context. This technological context is not necessarily prior art, but is intended to help in pointing out the disclosed inventions.
The Era of Downscaling
Since about 1960, the steady downscaling of integrated circuit minimum dimensions has permitted ever-increasing density, and thus an ever-increasing range of functionality at an ever-more favorable cost. This wealth of opportunity has permitted system designers to introduce many of the electronic products which have revolutionized industry and daily life in these decades. Continued downscaling steadily improves the available functionalities and pricing, and thus steadily challenges system designers. This fosters a continuing climate of active innovation and competition.
The most obvious index of downscaling is the steady reduction in the “minimum geometry” which can be specified for fabrication of an integrated circuit. This corresponds to a reduction in the size and spacing of the individual transistors, and thus steadily increases the number of transistors which can be fabricated in a given area. However, it is important to note that scaling has also provided exponential improvements in device speed and power dissipation, which has led to substantial enhancement of system performance. Thus, an end to the epoch of downscaling would drastically reduce the speed of progress in electronics.
Limitations of Semiconductor Microelectronics
The danger now in sight is that the downscaling of minimum geometries of transistor-based integrated circuits will eventually be brought to an end by a combination of problems related to devices, interconnections, noise, and reliability.1 The resulting saturation of circuit densities almost certainly implies a saturation of the historical exponentially downward trend in cost and volume per bit or function. 1These issues have been widely discussed; see, e.g., Chatterjee et al., 130, PROC. IEE 105 (1983), which is hereby incorporated by reference.
A technology-dependent issue is where existing ULSI (“ultralarge-scale integration,” i.e. semiconductor fabrication with minimum dimensions of a micron or less) will usefully end. From recent work, it is reasonable that this will occur in the 0.1 micron regime; scaling to just the 100 s of Å level may not be cost-effective in relation to the development costs of the technology. Thus, identifying an atomic-scale device technology seems the only approach worth the investment.
Several constraints are visibly converging to cut off the advantages of further scaling. While it is likely that clever process modifications can postpone the impact of some constraints, it does not seem likely that all can be avoided.
Alignment Tolerances
One of the basic problems is alignment tolerances: formation of features at a small minimum size λ does not imply that that minimum size can be used for fabrication of working circuits: it is also necessary to have alignment tolerances which are much smaller than λ (preferably well under λ/4). (Thus, a 0.8μ lithography process will typically have a specified alignment tolerance of ±0.15μ or less.)
With further scaling, this imposes several nonobvious difficulties. One is thermal stability, as discussed below.
Dopant Diffusion Lengths
Diffusion lengths scale approximately as (Dt)1/2, where t is time at the highest temperature, and D is a temperature-dependent diffusion constant characteristic of the dopant and the background material. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In the past decade, many accommodations have been made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely. For example, arsenic (or antimony) dopants are now used increasingly in place of phosphorus, but there is no suitale N-type dopant with significantly lower diffusivity than these two.
Punch-through, Doping Levels, Electric Fields, and Hot Electrons
A voltage applied across a semiconductor junction (in the reverse-bias direction) will naturally create a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, “punch-through,” i.e. uncontrolled current flow, may occur.
Higher doping levels will help to minimize the separations required to prevent punch-through. However, if the voltage change per unit distance is large, this creates a further difficulty.
A large voltage change per unit distance implies that the magnitude of the electric field is large. An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a “hot” electron, and may be sufficiently energetic to pass through an insulator. Thus, hot electrons can irreversibly degrade some common types of devices.
Isolation in a Monolithic Semiconductor Substrate
Conventional semiconductor integrated circuit technology uses a monolithic substrate which is all one crystal. Such substrates provide great advantages in processing. However, this device architecture poses some inherent difficulty with further scaling. One difficulty is lateral isolation of devices from each other. Another difficulty is leakage current scaling. Another difficulty is presented by the diffusivity of carriers within the substrate: free carriers (generated, e.g., by an alpha particle hit) can diffuse over many tens of microns to help neutralize a stored charge. Some attempts have been made to overcome these difficulties by using total isolation from the substrate, but to date such technologies have not demonstrated favorable economics of scaling.
Considerations in Further Downscaling
Theoretically, further downscaling of devices would still be achievable with the appropriate device technology, IF the approach could simultaneously address the interconnection, reliability, and implied fabrication limitations. Estimates based on abstract physical switching device models which are independent of specific device technologies indicate that several orders of magnitude in downscaling of device power in devices would be theoretically permitted,2 if an appropriate device technology could be found. The key to this search is to employ electronic phenomena which are characterized by dimensions much smaller than the depletion layer widths and diffusion lengths which provide the basis for conventional transistor function. 2See R. T. Bate, “VLSI Electronics” (N. G. Einspruch, ed.), Vol. 5, p. 359 (Academic Press 1982), which is hereby incorporated by reference.
Limitations of Semiconductor Nanoelectronics
Within the last decade, tremendous progress in semiconductor nanofabrication and nanoscale spatial and charge quantization phenomena has bridged the gap from the 0.1 micron regime to the ˜10 s of Å scale, and even to the atomic level with scanning probe techniques.3 These advances allow one to create electronic structures that exhibit manifest quantum and single electron effects. However, proposed solid state device implementations at this level suffer from three problems. The first is critical dimensional control. Electron devices which operate in this range must operate by tunneling, since a barrier (heterostructure, oxide, or otherwise) is a prerequisite for isolation in a 3-terminal device that can exhibit gain. However, electron tunneling is exponentially sensitive to atomic-layer fluctuations in the tunneling barriers, resulting in device characteristic variations unacceptable for large scale integration. Secondly, device embodiments utilizing discrete electron charging (single electron transistors, or SETs) suffer from reduced operating temperatures; for room temperature operation, 1 nm or less size junctions are required, dimensions which imply severe tunnel barrier fluctuation problems for solid state embodiments. Finally, none of these approaches address the interconnection and alignment problems. It is instructive to note that these investigations have had little impact on extending ULSI, due to the fundamental limitations of conventional semiconductor devices and fabrication. Fabrication at the nanoscale, and ultimately at the atomic level, of even the simplest structures (interconnects and contacts) is a daunting task. Techniques such as electron beam and STM4 lithography for pattern transfer appears to bottom out at ˜100 Å, due to the requirement of pattern transfer. Atomic manipulation with scanning probes has been demonstrated, but it is unlikely that this technique will be more than a laboratory curiosity since it is essentially a serial approach. (This criticism also holds for STM micromachined arrays, due to registration and access time limitations). 3See for example, NANOSTRUCTURE PHYSICS AND FABRICATION, edited by M. A. Reed and W. P. Kirk, Academic Press, 1989; and NANOSTRUCTURES AND MESOSCOPIC SYSTEMS, edited by W. P. Kirk and M. A. Reed, Academic Press, 1992; both of which are hereby incorporated by reference.4“STM” is a conventional abbreviation for scanning tunnelling microscope (or microscopy).
Solid state embodiments of quantum size electronic devices suffer from a number of problems. They are:
Dimensional Fabrication Tolerance: In a quantum device that utilizes quantum size effects, the intrinsic energy levels (and therefore the threshold voltage) are at least inversely proportional to the size of the device, dependent on the detailed shape of the device potential. If there are fabrication-induced dimensional variations, the quantum state energy will be different from device to device. The smaller the device becomes, the larger the voltage fluctuations. For many semiconductors, such as silicon and gallium arsenide, it is impossible to both make the device small enough such that the quantum energy level spacing is large compared to room temperature thermal energy, and large enough such that a fluctuation of a single monolayer does not unacceptably shift the threshold voltage.
Fabrication Tolerance Limits: Fabrication tolerance is critical when a tunnel barrier (semiconductor or metal oxide) is used. The current transmitted through the tunnel barrier is exponentially proportional to the tunnel barrier thickness, so again one has the limitation of changes of a single monolayer from device to device in a ULSI circuit will drastically change the output current, and therefore the input voltage to the next stage. The only way to reduce this intrinsic problem (other than a fabrication scheme which guarantees atomic precision) is to increase the barrier thickness to the point where a monolayer thickness fluctuation does not affect the overall current. However, this drastically reduces current density, and thus does not make a good device. Most useful semiconductor and metal oxide tunnel barriers are in the range 5–10 monolayers.
Contact Statistics: When one makes a quantum device, the contacts to the device must also be reduced to this dimension. If the ohmic contact between devices is made too small, the wavefunction of one device will overlap the second device. This has been demonstrated in high mobility two-dimensional gas layers, where the change of the wavefunction in one part of the layer remotely affected another part. This is not acceptable, since electron devices as we know them must have isolation from one to the next. This implies that the minimum distance between devices is the inelastic scattering length, which is approximately a few tens of nanometers in useful semiconductor materials. Since this defines a minimum contact volume (i.e., a few hundred cubic Ångstroms), we can estimate the number of dopant atoms in the contact, which for this size is only a few tens of dopant atoms. This means that the statistical fluctuations in the number (and position) will dramatically shift the voltage threshold.
Temperature and Voltage Limits: Quantum wave mechanical devices suffer not only from the above mentioned fabrication fluctuation problems, but also from low temperature/voltage intrinsic limitations. A wave mechanical interference device may be conceived where the output is modulated by an external gate or potential. However, destructive interference of the waves implies that the wave is monochromatic; this implies that only one subband can be used. Not only does this imply very low temperature operation (the electron energy distribution at the Fermi level must be much less than the room temperature thermal distribution), but the maximum conductance of the device is intrinsically very low (80 μS).
Proposed “Waveguide” Devices: A different proposed structure is the “waveguide” type of device, in which it has been suggested that the electron wavefunctions will remain in a standing wave pattern which can be changed by induccing a reactance shift at a control point (analogous to an RF stub tuner). However, this proposal has a difficulty due to the multiple subbands available for electrons in semiconductors: since the different subbands will typically have different effective wavelengths in a physical structure, the phase shifts which switch the lowest subband off will not necessarily switch off the higher subbands.
The Interconnect Problem: Even if a technology can be identified which solves the device scaling problem, the problems of interconnections and reliability will require revolutionary solutions. The “interconnect problem” is manifested as propagation delays in device interconnections that limit ultimate system performance. This is especially crucial for the complex logic circuitry of general-purpose processors. Though incremental evolutionary improvements in present transistor technology will surely continue, the resultant yield loss and subsequent increase in cost-per-function will eventually reach a minimum. An interesting example of these limitations is the problem of achieving large dynamic range alignment in this regime. Imagine that in the future one could achieve 100 Å pitch and size active devices, which corresponds to approximately 1 part in 107 dimensional resolution when approximately conserving present chip dimension, for cost and function scaling. This implies optimistically demanding less than 0.05° C. temperature gradients during any fabrication step requiring alignment, which are clearly untenable dimensional and thermal requirements.
The ultimate device technology (if it exists) at this scale, independent of device embodiment, will thus solve the interconnection problem and will be predominantly self-aligned.
The generic properties of a technology which addresses the critical problems can be detailed as follows:                a key innovation must be the solution to the interconnect problem.        The fabrication technology must be predominantly self-aligned, perhaps non-lithographic and self-limiting.        Scaling to the atomic level, and room temperature operation, is desired.        
Conjugated Conductive Polymers5 5In this application, the term “conductive polymer” is used only to refer to conjugated polymers (in which the conjugation of π orbitals leads to electron delocalization, and hence to the potential for high conductivity with appropriate doping). Unfortunately, this term is also used, in engineering literature, to refer to a quite different class of materials, in which a conductive particulate material (typically graphite or metal fibers or powder) is incorporated as filler in a nonconducting polymer matrix.
A vast amount of work has been done, by chemists and physicists, in studying the structure, synthesis, and electronic behavior of conjugated conductive polymers.6 For many years these materials were not candidates for commercial applications; but more recently newer families of materials have been identified. 6See generally all of the articles in the two-volume set Handbook of Conducting Polymers (ed. Skotheim 1986), and the references cited in those articles; all of which are hereby incorporated by reference.
π-orbitals and Extended States
“Conjugated” conductive polymers are those which have overlapping π-orbitals. The resulting extended molecular orbitals provide a pathway through which electrons can travel, IF an external field is applied and IF excess electrons are present, to provide conduction.
Note that conjugated bonding is not itself sufficient to provide good conduction. Therefore, conductive polymer molecular structures often include “dopant” atoms which are selected to provide an adequate carrier density for conduction.
Improvements in Conductivity
Modern conductive polymer compounds have achieved bulk conductivities of greater than 1 Scm−1. This begins to be comparable with metals. (For example, the bulk conductivity of copper is slightly less than 600 Scm−1.)
Improvements in Stability
Dramatic improvements have occurred in chemical stability of conductive polymers. The first extensively studied material was polyacetylene, which is unstable and highly reactive with oxygen, but a succession of investigators have found more stable and less reactive materials with higher conductivities, as detailed below.
Innovative Systems. Modules, Circuits, Devices, and Methods
The present application discloses a novel technological approach which fits these requirements, and can lead to a new era in ultra-dense electronic systems.
Among the disclosed innovations is self-aligned spontaneous assembly of chemically synthesized interconnects, active devices, and circuits. This is a revolutionary approach for spontaneously assembling atomic scale electronics. It attacks the interconnection and critical dimension control problems in one step, and is implicitly atomic scale. Concurrently, the approach utilizes an inherently self-aligned batch processing technique which addresses the ultimate fabrication limitations of conventional ULSI.
There has been sporadic discusssion of molecular electronic devices for some years now. However, one key deficit of all previous proposals is their failure to solve the problem of achieving electrical GAIN in a molecular electronic device. The technology disclosed below provides a true gain modulation, by modulating the electron wavefunction of a polymeric conductor.
The innovative technology disclosed herein also radically improves the economics of downsizing electronic devices. In conventional semiconductor technology, the cost per transistor is no longer decreasing with reduced size; but the disclosed innovative technology returns to a regime of more favorable cost evolution.
The innovative technology disclosed herein provides an inherently very high degree of self-alignment in processing. Moreover, this new technology is inherently very well suited to batch processing. Many of the problems of fabrication tolerance, which limit the further progress of conventional methods, are solved in the new technology by chemical purification and selection techniques.
New Interconnect Technology
Among the many innovations disclosed herein is a new self-aligned integrated circuit interconnect technology which uses conductive polymers. This technology has many features in common with the active device embodiments described below, but can be exploited independently of those embodiments.
Self-Assembling Wires
There exist non-semiconductor candidates for atomic scale electronic structures which are presently at the molecular level. Since the 1970s, researchers have been exploring 1D conductive organic polymers, such as polyacetylene. Advances in synthesis have identified more promising candidates, such as diphenylpolyene, polythyolenes, polyarylenevinylene, polyarylene, polyphenylene, and polythiophenes. Conductivities of these wires (such as doped polyacetylene) have approached that of copper.7 These organic chains can have long electron delocalization lengths; for example, delocalization lengths of 20–34 atoms can be calculated from diphenylpolyene results,8 and ˜50 Å for polythiophenes.9 7See Chiang et al., 100 J. AM. CHEM. SOC. 1013 (1978), which is hereby incorporated by reference.8See the paper by C. W. Spangler which was presented at The 2nd International Conference on Molecular Electronics—Science and Technology, 15–19 Dec. 1991, St. Thomas, USVI (unpublished), and which is hereby incorporated by reference.9See the paper by J. Tour presented at PROCEEDINGS OF THE2ND INTERNATIONAL CONFERENCE ON MOLECULAR ELECTRONICS SCIENCE AND TECHNOLOGY, 15–19 Dec. 1991, St. Thomas, USVI (unpublished), which is hereby incorporated by reference.
Though the synthesis of 1D molecular wires has been known for some time, the inability to manipulate and assemble organic structures into useful complexes in a manner analogous to semiconductor devices has hindered any application toward electronics. The isolation and measurement of a single organic 1D wire, a key step toward electronic utilization of conductive polymers, has yet to be demonstrated (though the conductivity of large assemblages of the material has been measured). Yet the utilization of the atomic-scale control inherent in organic synthesis could provide an elegant solution to the fundamental fabrication limitations described previously.
The present application presents a new approach which combines molecular synthesis and nanofabrication. We take a conductive polymer, and attach (“functionalize”) onto the ends a compound that can selectively attach to a metal probe. Numerous examples of these “self-assembling” compound/metal pairs are known; for example, n-alkanethiols onto Au, isonitrile onto Pt, and alkanecarboxylic acid onto aluminum oxide.10 This is in essence a conducting string with sticky ends, which could bridge a gap between metallic contacts (of the selective metal). By fabricating (by E-beam or ST-M) closely-spaced metallic contacts, the molecular wire can be spontaneously deposited from solution. Note that if the molecular wire is synthesized with different end groups on opposing ends, the polarity of the attachment can be defined. The specific contact resistance of such an ohmic contact is not yet precisely known, though the large value of the bond energies imply this may not be a problem; for the organic thiolates and Au, this is 40–45 kcal/mole. These “selective-attachment conducting polymers” (specifically, conjugated organic oligomers with functionalized selective attachment termini) provide a technique for spontaneously generating contacts between metallic endpoints, at the molecular scale (10–100 Å). 10See the paper by G. M. Whitesides and P. E. Laibinis at 6 LANGMUIR 87 (1990), which is hereby incorporated by reference.
An advantageous application is for simple self-aligned interconnects; given a device with metal A on one terminal (for example, collector), and a second device with metal B on one terminal (for example, base), a molecular wire with end groups A′ and B′ (which attach selectively to A and B, respectively) can bind selectively to make an interconnect, without a lithography step. Though we will see that interconnects are not the most important application, this spontaneous “lock-and-key” concept is the basic ingredient. Also note that this process is, to a degree, length dependent. Interconnections of contacts separated by longer than the designed molecular wire length are prevented. An important technology issue is the nuisance of unwanted binding of the polymers other than at the terminal ends. It appears that this concern can be solved for large metallic contacts (other than simple binding posts) by either selective exposure of the metal (i.e., in the simplest case by via holes) through an insulating overlayer coating at only the contact points desired, or by post-attachment scavenging of the unwanted dangling molecular wires.
Selective Auto-Connection to Terminals
The disclosed process innovations provide a self-aligned connection of molecular “wires” to their target terminals. If the deposition process is allowed to go to completion, the number of polymer chains connected in parallel will be determined by the available area of the semiconductor or metal contact which the chains are attaching to.
Active Device Operation
One class of sample embodiments operates using the principle of resonant tunnelling.
FIG. 1A shows a resonant tunnelling device in the on-state. Note that an energy level in the well region provides an allowed transition for electrons which tunnel through the barrier into the well. Such electrons can then tunnel through the second barrier to a region of lower potential, providing a net current.
FIG. 1B shows the device of FIG. 1A in the off-state (after the potential of the base has been shifted). In this state the well no longer has an allowable energy state at the potential of incoming electrons. Therefore, normal conduction electrons cannot tunnel through the two barriers sequentially.
These Figures provide a simple schematic representation of a principle of operation which has been extensively analyzed, and which has been realized in heterojunction semiconductor devices. In such devices, the well region must be physically very small to produce the needed separation of allowable energy states, and these small dimensions cause the fabrication difficulties reviewed above.
However, the innovations disclosed in the present application provide a different way to achieve the same principle of operation (and also other principles of operation). Polymeric molecular structures are manipulated to produce combinations of well and barrier regions, with connections so that the well and/or barrier potentials can be manipulated.
FIG. 4A shows the spatial variation of conduction band (CB) and valence band (VB) energy levels across a first example monomer unit which can form conjugated conductive polymer structures. FIG. 4B shows the spatial variation of conduction band (CB) and valence band (VB) energy levels across a second example monomer unit which can form conjugated conductive polymer structures. FIG. 4C shows how, when two such monomer units are chemically combined, the resulting dimer structure has a band structure which produces a barrier-well-barrier-well-barrier profile.
FIGS. 5A and 5B are a corresponding pair of drawings of two states of operation of a novel molecular electronic device.
FIG. 5A shows the ON state. In this state an energy level in the well region is aligned with the energy level of incoming electrons, and thus resonant tunnelling can occur, to produce a net flow of electrons from the “emitter” terminal through to the “collector” terminal.
FIG. 5B shows the OFF state. In this state a different potential has been induced at the “base” terminal. This induced potential propagates, through the chain X, to change to energy levels in the well region. As a result of this change, no energy level in the well region is aligned with the energy level of incoming electrons, and thus resonant tunnelling does not occur, and therefore current flow does not occur between the “emitter” terminal and the “collector” terminal.
Modulation of Conductor's Conductivity
With a conductive polymer (unlike a semiconductor structure) there are two ways to change the conductivity of the structure. FIGS. 5A and 5B show one architecture, in which the well potential is modulated to achieve gated resonant tunnelling. However, another alternative is to modulate the BARRIER height, as shown in FIGS. 2A and 2B. In this alternative, the modulator chain would be coupled to a barrier location rather than to a well location.
The “Base Isolation” Barrier
To connect the modulator chain to the conductor chain, a coupling unit is preferably used which corresponds to a well in the primary conductor chain. From the base connection point, the modulator chain is (in the presently preferred embodiment) highly conjugated for short period; then a relatively high barrier is interposed, then a well, then a lower barrier; then the modulator chain is conductive for as long as needed. The barrierhigh-well-barrierlow structure serves, in effect, as a base isolation barrier. Note that gain would not be possible without some form of “base isolation.” Thus, this feature of the architecture gives substantial advantages.
Electrical Asymmetry of the Active Device
To get electrical asymmetry between Emitter→Collector and Collector→Emitter operation, different barrier heights can be used on different sides of the modulated tunnelling region. Moreover, the position of the modulated tunnelling region within the conductive oligomer chain can easily be made asymmetric if desired.
Connecting Signals into the Coupling Chain
Several methods are disclosed for coupling an input signal into the modulator side-chain of an oligomeric active device. The simplest connects the side-chain to an electrical contact. Another disclosed method uses a photosensitive compound to generate a voltage shift under illumination. Another disclosed method uses direct coupling of the modulator side-chain (the “base”) of one active device to the output chain (the “collector”) of another.
Also disclosed is a self-aligned contact process for preparing metal pads for the oligomeric conductors to bond to.
Inorganic Starting Structure
Preferably a semiconductor integrated circuit structure provides the starting point for fabrication of moecular devices. The conventional structure provides a transition from macroscopic signals down to the small magnitudes characteristic of molecular electronics. In particular, conventional integrated circuit structures can advantageously provide input ESD protection and output drivers.
Isolation
The isolation problem is not nearly as severe as in semiconductor devices, since there is no continuous substrate for carriers to diffuse through. Conduction normally occurs along a single molecule, and the connections of those molecules are largely defined by the formation process.
Device Density
Note that the technologies disclosed herein are inherently suitable for 3D fabrication—as opposed to any planar technology, in which more layers implies more process steps.
Interconnect Density
The novel interconnect technologies disclosed herein provide self-aligned interconnects which are length-constrained, but are NOT limited to line of sight. For example, a molecular electronic active device could even be positioned in an undercut trench if desired.
Configuring SSI-eguivalent Gates
It is also easy to configure devices with multiple inputs. For example, the detailed structure of a NOR gate is described below.
Passivation
Not all conductive polymers are as reactive as polyacetylene, but all are at least somewhat prone to react with O2. (In general, doped polymers are more reactive toward owygen than are the corresponding undoped polymers.) However, advances in conductive polymer research in the 1980s revealed that several families (particularly modified thiophenes) are much more stable, and much less reactive toward oxygen. For long-term use, it is still necessary to package such materials in an anaerobic light-shielded package, but this is easily done as described below.
Available Principles of Operation
The electronic transport mechanisms for quantum-sized systems with tunnel barriers are either; a) tunneling through localized states (i.e., resonant tunneling), or; b) hopping (with attendant issues of Coulomb blockade); or, c) a combination of both.
Resonant tunneling (as schematically shown in FIGS. 2A–2C) is a conduction mechanism which depends on quantum mechanical tunneling through a quasi-bound quantum-confined state. The simplest embodiment is a quantum well cladded by thin tunnel barriers. Electrons from the emitter of such a structure tunnel through the first barrier into the central well region, and then quickly tunnel out. If the central quantum state is made to be energetically misaligned with the incoming emitter electrons, such as by a base potential applied to the central quantum well, the current is dramatically reduced. By this mechanism, a transistor with gain can be produced. Such embodiments have been extensively demonstrated in semiconductor devices, but not in molecular electronic structures.
Hopping, or Coulomb blockade, is a different conduction mechanism, wherein the structure can be thought of as a series of small capacitors. If the structure is sufficiently small, the charging energy of the capacitor, Ec=e2/2C, can be so large that it is energetically unfavorable for 2 or more electrons to be on the central terminal; thus, a single electron at a time “hops” through the structure. FIGS. 3A–3C schematically show this mode of operation, and FIG. 3D shows the corresponding electrical model.
The hopping mechanism is differentiated from resonant tunneling mainly by current density; if the collector barrier is sufficiently thin, electrons quickly tunnel through the structure, so Coulomb blockade never has a chance to take effect; thus, resonant tunneling is the mechanism. If the collector barrier is thick and/or high, the electron resides in the central region for a long time, and thus Coulomb blockade occurs.
The advantage of resonant tunneling is that high current density and large gain are possible. In Coulomb blockade, the ultimate limit of an electron device (i.e., a single electron device), the current density is low, and it is as yet unclear that large gain can be achieved in such a device.
According to one embodiment of the present invention there is provided:
A system comprising:
    a master clock circuit, and an optical output driver connected to follow the frequency and phase of said master clock circuit;    a plurality of electronic circuits, on one or more integrated circuits, wherein plural ones of said electronic circuits include semiconductor active devices configured as output drivers,    and wherein plural ones of said electronic circuits include first and second conductive contacts thereof and a photoconductive oligomeric structure connected therebetween;    and where light from said optical output driver is optically coupled to multiple ones of said photoconducive oligomeric structures in multiple ones of said circuits.
According to another embodiment of the present invention there is provided:
A circuit comprising:
    a semiconductor integrated circuit, comprising semiconductor driver devices, and electrically configured to be connected to first, second, and third contacts;    a first molecular electronics device, electrically configured to receive a first input signal and to provide a conductivity, between said first and third contacts, which is modulated in accordance with said first input signal;    a second molecular electronics device, electrically configured to receive a second input signal and to provide a conductivity, between said second and third contacts, which is modulated in accordance with said first input signal;    a voltage detection circuit, electrically connected to detect the voltage of said third contact and provide a corresponding output;    whereby said output of said voltage detection circuit provides a signal which is equivalent to a NOR of said first and second input signals.
According to another embodiment of the present invention there is provided:
A picoelectronic device comprising:
    first and second conductor chains, each comprising multiple monomor units having mutually conjugated bonding;    a first barrier region, connected to said first conductor chain, said first barrier having a potential energy for electrons which is less favorable than that of said first conductor chain;    a second barrier region, connected to said second conductor chain, said first barrier having a potential energy for electrons which is less favorable than that of said second conductor chain;    a well region, connected to said first and second barrier regions, said well region having a potential energy for electrons which is more favorable than that of said first and second barrier regions;    a third barrier region, connected to said well region, said third barrier having a potential energy for electrons which is less favorable than that of said well;    a third conductor chain, comprising multiple monomor units having mutually conjugated bonding, and operatively connected to said well region through said third barrier region;    whereby changing potentials applied to said third chain can effect modulation of currents between said first and second chains.
According to another embodimenmt of the present invention there is also provided:
An integrated circuit structure, comprising:
    a plurality of transistors;    a plurality of thin-film conductor interconnects, interconnected to form electronic circuits in a predetermined electrical configuration;    a plurality of pairs of contact pads, connected to said thin-film conductor interconnects, each adjacent pair of contact pads being interconnected being electrically connected only by a conductive oligomer of a precisely predetermined number of units.
According to another embodimenmt of the present invention there is also provided:
An integrated circuit structure, comprising:
    a plurality of transistors;    a plurality of thin-film conductor interconnects, interconnected to form electronic circuits in a predetermined electrical configuration;    a plurality of pairs of contact pads, connected to said thin-film conductor interconnects, each adjacent pair of contact pads being electrically connected only by a conductive oligomer of a precisely predetermined number of units.
According to another embodimenmt of the present invention there is also provided:
An integrated circuit structure, comprising:
    a plurality of semiconductor transistors;    a plurality of thin-film conductor interconnects, interconnected with said semiconductor transistors to form electronic circuits in a predetermined electrical configuration;    a plurality of pairs of contact pads, connected to said thin-film conductor interconnects;    a plurality of molecular electronic active devices, each including a conductive oligomer connecting one of said contact pads, and a barrier-well-barrier structure connected to modulate the conductivity of said conductive oligomer.
According to another embodimenmt of the present invention there is also provided:
An integrated circuit structure, comprising:
    a plurality of transistors;    a plurality of thin-film conductor interconnects, interconnected to form electronic circuits in a predetermined electrical configuration;    a plurality of pairs of contact pads, connected to said thin-film conductor interconnects, each adjacent pair of contact pads including a first pad of a first conductive material and a second pad of a second conductive material, and being electrically connected only by a conductive oligomer of a precisely predetermined number of units.